A Driving Loss and Speed Co-Optimized Series Resonant Gate Driver with Novel Time Segmented Methodology for High Frequency SiC MOSFETs

Resonant gate drive (RGD) is the more efficient solution to drive SiC MOSFETs at high switching frequencies with effective gate driver energy saving. It adjusts driving characteristics from RC step response to RLC resonant response at the risk of reduced power transistors' switching speed and increased switching loss. Resonant inductor becomes the most important component in RGD design and is mutually restraint for gate driver loss reduction and power transistor switching characteristics improvement. Current studies on RGD vaguely uses MOSFET input capacitor (Ciss) from datasheet or total gate charge (Qg) to analyze driver characteristics. The non-linear feature brought by MOSFET miller capacitor is completely ignored, which leads to un-optimized resonant inductor selection and poor understanding in RGD influence on MOSFET switching behaviors. To overcome these issues, a novel time segmented methodology is proposed to provide comprehensive analysis of RGD and understand its impacts on different aspects. The driving loss and SiC switching speed co-optimized series resonant gate driver is demonstrated with 25.5% saving on gate driver loss and 44.4% improvement in driving speed at 200 kHz switching frequency.